As a solid-state imaging device on the basis of the CMOS technique, there is known one comprising photodiodes, charge-voltage converting circuits, holding circuits, and a readout circuit (refer to Patent Document 1). In this solid-state imaging device, charge quantities corresponding to incident light amounts on the photodiodes are generated at the photodiodes, and voltage values corresponding to charge quantities are output from the charge-voltage converting circuits, and the voltage values output from the charge-voltage converting circuits are held by the holding circuits. One readout circuit is provided for a plurality of sets, each of which consists of a photodiode, a charge-voltage converting circuit, and a holding circuit, and voltage values successively output from the holding circuits of the respective sets are read out through the readout circuit.
Generally, the readout circuit includes an amplifier, a capacitor, and a switch. The capacitor and the switch are connected in parallel to each other, and connected between the input terminal and the output terminal of the amplifier. In the readout circuit, when reading out voltage values successively output from the holding circuits of the respective sets, the capacitor is discharged by closing of the switch only for a given period, and during the subsequent period of opening of the switch, charge quantity corresponding to the voltage value output from the holding circuit of a certain set is accumulated in the capacitor, and a voltage value corresponding to the accumulated charge quantity is output. This operation of the readout circuit is performed for each time of reading out of the voltage values successively output from the holding circuits of the respective sets.    Patent Document 1: Japanese Published Unexamined Patent Application No. H07-239994